There has been known a phase calibration circuit which uses a data block including a data body and detection information for detecting an error, and acquires the data block transferred by using a reference clock signal (refer to Patent Document 1). A reception clock generating unit generates a plurality of clock signals including at least a first clock signal whose phase is shifted with respect to the reference clock signal, a second clock signal whose phase is advanced with respect to the first clock signal, and a third clock signal whose phase is delayed with respect to the first clock signal. A determination unit acquires the data block in accordance with the plurality of clock signals, and determines whether or not a read error is occurred, by using the detection information. Subsequently, the determination unit outputs a plurality of determination results including at least a first determination result obtained by determining the data block acquired in accordance with the first clock signal, a second determination result obtained by determining the data block acquired in accordance with the second clock signal, and a third determination result obtained by determining the data block acquired in accordance with the third clock signal. A phase adjusting unit instructs the reception clock generating unit to adjust the phase of the first clock signal, according to the plurality of determination results.
There has been known a transmitting device which transmits data and a clock to a receiving device (refer to Patent Document 2). A data transmitting unit transmits data to the receiving device. A clock transmitting unit transmits a clock to the receiving device. A reception unit receives the data from the receiving device. A control unit controls the data transmission performed by the data transmitting unit, and the clock transmission performed by the clock transmitting unit. The control unit makes the data transmitting unit transmit, to the receiving device at a predetermined timing, each of ordinary data, calibration data for detecting a data reception state or a clock reception state in the receiving device, calibration start instruction data which instructs the receiving device to start the transmission of the calibration data, and transmission instruction data which instructs the receiving device to transmit calibration sample data which is obtained when the receiving device samples the calibration data. When the reception unit receives the calibration sample data transmitted from the receiving device, the control unit performs control, based on the received calibration sample data, any one or more of adjustment of a phase between the data transmitted by the data transmitting unit and the clock transmitted by the clock transmitting unit, adjustment of an amplitude of the data transmitted by the data transmitting unit, adjustment of a duty of the data transmitted by the data transmitting unit, and adjustment of a duty of the clock transmitted by the clock transmitting unit.    Patent Document 1: Japanese Laid-open Patent Publication No. 2011-90361    Patent Document 2: Japanese Laid-open Patent Publication No. 2011-91745
When a clock signal is delayed, a phase of the clock signal is shifted with respect to data. When the phase-shifted data is transmitted, an occurrence rate of a reception error increases. In particular, the occurrence rate of the reception error increases when a frequency of the clock signal becomes high.